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L8150
Brushless motor predriver
Feature

Integrated Predriver IC for 3 phase BL motor. Integrated Smooth driving concept with sinusoidal driving waveforms. BCD5 technology 0.6mm. Package: SO28. Three Hall effects, differential input comparators. Integrated Undervoltage lockout (VCC). PWM output duty (voltage) control / Torque optimizer / protection functions PWM carrier 17kHz min / integrated dead time

SO28
External HVIC bootstrap capacitor refresh function during 120 degree drive (rectangular drive). This means both upper and lower chopping and low side current recirculation for rectangular drive. Current limiter circuit VCC lower voltage protection / VDC over voltage protection circuit / Hall sensor fail protection FAULT signal output
Functions

C-MOS level predriver output (high active) Free Run function Dead time (3 values selectable) Sinusoidal waveform PWM logic Detected rotation speed (FG) output terminal PWM duty control by analog input (KVAL control) Forward/backward rotation input terminal (FR) / rotation direction detection output terminal (DM) Thermistor connection terminal (thermal protection) Torque optimizer terminal controlled by analog voltage input V regulator output terminalExternal HVIC bootstrap capacitor pre-charge function
Description
The L8150 device is a motor predriver intended to drive brushless fan motors with Hall effect sensors. The device, realized in BCD5 0.6mm mixed technology, is characterized by a mostly digital architecture assuring high integration density and high test coverage. The L8150 with few external components forms a complete control circuit, since the smooth driver logic is fully integrated: its peculiar driving solution (smooth driving) allows a very low current ripple and speed control even at low rotation speeds.

Order codes
Part number E-L8150 E-L8150TR Temp range, C -20 to 95 -20 to 95 Package SO28 SO28 Packing TUBE Tape & Reel
March 2006
Rev 1
1/37
www.st.com 1
Contents
L8150
Contents
1 Block diagram & pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 4
Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Drive stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hall Sensor Input Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External HVIC Bootstrap Capacitor Initialization . . . . . . . . . . . . . . . . . . . 14 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 5.3 Free-Run (FS) and Reset (SD) functions . . . . . . . . . . . . . . . . . . . . . . . . . 16 Smooth Drive and Control logic description . . . . . . . . . . . . . . . . . . . . . . . 16 Speed Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Precharge and hall effects filtering time description . . . . . . . . . . . . . . 24
6.1 6.2 Startup sequence with FS signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Startup sequence with SD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/37
L8150
Contents
8 9 10
Input Output Pins Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
List of tables
L8150
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply Voltage Terminal VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Regulator Output Terminal Vreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver Output Terminal UH,VH,WH,UL,VL,WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dead Time Select Terminal SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN . . . . . . . . . . . . . . . . . . . . . . . 9 Torque Optimizer Input Terminal T.O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Over Current Sense Input Terminal R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forward Backward Select Terminal FR (note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Sense Input Terminal TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FG Output Terminal FG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OSC Terminal OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OP Amp Input Output Terminal INTin+, INTin-, INTout (note 3, note 4). . . . . . . . . . . . . . . 10 Over Voltage Protection Terminal OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FAULTS Output Terminal FAULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Rotation Direction Detection Terminal DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 KVAL Contro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Phase Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 different values of the signal Pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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L8150
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Kval control by VSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External circuit for Vsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 16 bit counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Smooth drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase shift vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Smooth Drive Pattern (Reverse). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rectangular drive pattern (forward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rectangular Drive Pattern (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Filtering circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Startup sequence forced by FS comparator, assuming the motor is not rotating . . . . . . . . 24 Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction imposed by the FR signal: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . 26 Startup sequence forced by FS comparator, supposing the motor rotating too quickly . . . 27 Startup sequence forced by SD, supposing the motor stopped . . . . . . . . . . . . . . . . . . . . . 28 Startup sequence forced by SD, supposing the motor rotating quickly in the direction imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup sequence forced by SD, supposing the motor rotating quickly in the direction not imposed by the FR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup sequence forced by SD signal, supposing the motor rotating too quickly . . . . . . . 30 Basic motor control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3 phases motor control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pins: TSD, OV, SDT, INTinN, INTinP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: TO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: INTout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pins: FG, DM, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ESD clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Recirculation diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: FR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: HWN, HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: HUN, HUVP, HVN, HVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pins: UH, UL, VH, VL, WH, WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO-28 Mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Block diagram & pins description
L8150
1
1.1
Figure 1.
Block diagram & pins description
Block diagram
Block diagram
1.2
Figure 2.
Pins description
Pins connection (top view)
RF WH WL VH VL UH UL SDT HUP UHN HVP HVN HWP HWN 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D01IN1259
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND VCC VREG TO INTOUT INTINN INTINP FAULT OSC FR TSD OV DM FG
6/37
L8150 Table 1.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Block diagram & pins description Pins description
Pin RF WH WL VH VL UH UL SDT HUP HUN HVP HVN HWP HWN FG DM OV TSD FR OSC FAULT INTinP INTinN INTout TO VREG VCC GND External sense resistance pin W bridge high-side MOS output command W bridge low-side MOS output command V bridge high-side MOS output command V bridge low-side MOS output command U bridge high-side MOS output command U bridge low-side MOS output command Dead time selection input pin Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Hall sensor differential input Multiplexed Hall effects output Motor direction detected output Over-voltage comparator input External thermal shutdown input Forward/backward rotation input External 20.5k polarization resistance pin Fault signal output Error amplifier reference input pin Error amplifier negative input pin Error amplifier output Torque optimizer analog input Internal 5V regulator output External 15V supply Ground pin Function
7/37
Electrical specifications
L8150
2
2.1
Table 2.
No. 1 2 3 4 5 6 7
Electrical specifications
Absolute maximum ratings
Absolute maximum ratings
Item VCC supply voltage FG terminal voltage FAULT terminal voltage DM terminal voltage FG, FAULT, DM currents RF voltage Other pin voltage Symbol VCC VFG VFAULT VDM Iod VRF VCC FG FAULT DM FG, FAULT, DM RF SDT,HUP,HUN,HVP HVN,HWP,HWN,OV,TSD FR,INTinN,INTinP,TO SDT,HUP,HUN,HVP HVN,HWP,HWN,OV,TSD FR,INTinN,INTinP,TO Topg Tj Tstg all pin all pin 2000 V Human body model Terminal Value 20 -0.3/20 -0.3/20 -0.3/20 15 -5 to VREG -0.3 / 6 Unit V V V V mA V V Maximum current Remark
8
Inject current Operating ambient temp. Junction temp. Storage temp. Latch up tolerance ESD tolerance
5
mA
9 10 11 12 13
-20/+95 150 -55/+150 200 200
C C C mA V Machine model
2.2
Table 3.
No. remark 1
Operating condition
Operating condition
item symbol terminal MIN TYPE MAX unit
supply voltage
VCC
VCC
12.75
15
17.25
V
8/37
L8150
Electrical characteristcs
3
Electrical characteristcs
Tamb = 25 C, VCC =15V, VREG = 5V unless otherwise specified
Table 4.
No. 1
Supply Voltage Terminal VCC
Item Symbol ICC1-1 Terminal VCC Min Typ 10.0 Max 20.0 Unit mA Remark
current consumption 1-1
Table 5.
NO. 1 2 3 4
Regulator Output Terminal Vreg
Item Symbol VREG VREG1 VREG2 VREG3 Terminal VREG VREG VREG VREG Min 4.7 Typ 5.0 40 5 0 Max 5.3 100 30 Unit V mV mV mV/C VCC1=12.75 to 17.25V IO=5 TO 20mA (note 1) Remark
output voltage voltage variation load variation thermal coefficient
Table 6.
No. 2 4
Driver Output Terminal UH,VH,WH,UL,VL,WL
Item Symbol VOH VOL Terminal UH,... UH,... Min 3.70 0.40 Typ Max Unit V V Remark IOH=-2.5mA IOL=2.5mA
H level output voltage 2 L level output voltage 2
T
Table 7.
No. 1 2 3
Dead Time Select Terminal SD
Item Symbol VSDTH VSDTM VSDTL Terminal SDT SDT SDT Min 9/10 Vreg 4/10 Vreg 0 Typ Max Vreg 6/10 Vreg 1/10 Vreg Unit V V V Remark dead time =0 usec dead time=1.5usec (Tdeadtime=15xTck) dead time=1.0usec (Tdeadtime=10xTck)
H level input voltage M level input voltage L level input voltage
Table 8.
No. 1 2 3 4 5 6 7
Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN
Item Symbol IHB(HA) VICM VI VIN(HA) VSLH(HA) VSHL(HA) Terminal HUP,... HUP,... HUP,... HUP,... HUP,... HUP,... HUP,... Min -2 0.50 0.00 50 20 5 -25 30 15 -15 50 25 -5 3.00 5.00 Typ Max Unit uA V V mVp-p mV mV mV for hall device for hall IC, note 2 Remark
input bias current common mode input range input voltage range hall input sensitivity hysteresis width hysteresis L -> H hysteresis H -> L
9/37
Electrical characteristcs Table 9.
No. 1 2 3
L8150
Torque Optimizer Input Terminal T.O.
Item Symbol Terminal T.O. T.O. T.O. Min Typ 15/25Vreg 0 100 mV Max Unit Remark
max analog conversion input min analog conversion input hysteresis
Table 10.
No. 1
Over Current Sense Input Terminal R
Item Symbol VRF Terminal RF Min 0.45 Typ 0.50 Max 0.55 Unit V Remark
over current sense level
Table 11.
No. 1 2 3 4
Forward Backward Select Terminal FR (note 7)
Item Symbol VIH (FR) VIL (FR) Ru (FR) VIS (FR) Terminal FR FR FR FR Min 2.0 0.0 -20% 0.2 50.0 0.3 Typ Max VREG 1.0 +20% 0.4 Unit V V kOhm V Remark
H level input voltage L level input voltage pull-up resistor to VREG hysteresis width
Table 12.
No. 1 2
Thermal Sense Input Terminal TSD
Item Symbol VIH (TSD) Vhy (TSD) Terminal TSD TSD Min 2.60 0.20 Typ Max 3.00 0.30 Unit V V Remark
TSD Threshold Hysteresis
Table 13.
No. 1 2
FG Output Terminal FG
Item Symbol VFGL IFGleak Terminal FG FG Min Typ Max 0.50 10 Unit V uA Remark Io=15mA, open drain Vo=16.5V
Output saturation voltage Output leak current
Table 14.
No. 1 2
OSC Terminal OSC
Item Symbol Vosc Fpwm Terminal OSC 18k Min Typ 1.235 20.4k Max Unit V Hz Remark R=20.5kohm (Class E96), Fsys=512*Fpwm 17kHz - 21kHz for Tj=0 to 125 deg
Current setting PWM frequency
Table 15.
No. 1 2 3 4
OP Amp Input Output Terminal INTin+, INTin-, INTout (note 3, note 4)
Item Symbol VoH (INT) VoL (INT) IB (INT) Terminal INTout INTout INTin+, -0.2 Min 4.0 Typ Vreg2-0.2 Max Vreg 1.0 0.2 Unit V V uA V Remark Io=1mA Io=1mA
H level output voltage L level output voltage input bias current offset
10/37
L8150 Table 16.
No. 1 2
Electrical characteristcs Over Voltage Protection Terminal OV
Item H level input voltage (operative) Hysteresis width Symbol VIH (OV) VIS (OV) Terminal OV OV Min -6% 0.3 Typ 3.0 Max +6% 0.4 Unit V V Remark
Table 17.
No. 1 2 3
Low Voltage Protection
Item Symbol VIL (LV) VIH (LV) VIS (LV) Terminal LV LV LV Min 10 10.35 0.35 Typ 11 11.50 0.50 Max 12 12.65 0.65 Unit V V V Remark
operation voltage release voltage hysteresis width
Table 18.
No. 1 2
FAULTS Output Terminal FAULTS
item symbol VFaultsL IFaultsleak terminal FAULTS FAULTS MIN TYP MAX 0.50 10 unit V uA remark Io=15mA, open drain Vo=17.25V
output saturation voltage output leak current
Table 19.
No. 1 2
Rotation Direction Detection Terminal DM
Item Symbol VDML IDMleak Terminal DM DM Min Typ Max 0.50 10 Unit V uA Remark Io=15mA, open drain Vo=17.25V
output saturation voltage output leak current
Table 20.
No. 1 2 3 4
KVAL Contro
Item Symbol Terminal INTout INTout INTout INTout Min -3% -3% -7% Typ 4.5Vreg/5 3.7Vreg/5 0.7Vreg/5 70.0 Max +3% +3% +7% Unit V V V mV Remark Note 3 Note 3 Note 3
l
FS threshold voltage KVAL Min voltage KVAL max voltage FS Hysteresis
Note:
1 2 3
If 20mA is a problem for design because of power dissipation etc., it can be reduced to something like 5mA one input is set at 2.5V by means of a resistor divider. The other input moves from 0V to Vreg. The Hall comparator must operate correctly for all its input range. Opamp need to be designed to meet with Kval control by VSP. External circuit for Vsp control (example) is shown in following Figure 4. The tolerance at Vsp including external resistor (E96) is as follows: mini typ max V1(V) 0.85 1.23 1.6 V2(V) 1.7 2.1 2.5 V3(V) 4.9 5.4 6.1 FR and INTin+ are used to set test mode as follows: Test mode is set by 8 events (clock rising edges) on FR during INTin+>4.5 (Power is kept as high-impedance for INTin+ > 4.5 until 7th event occur) (counter for FR is reset by INTin+ < 4.5)
4
11/37
Electrical characteristcs Figure 3. Kval control by VSP
L8150
Figure 4.
External circuit for Vsp control
INT amp network (suggested)
90.9K Vsp 53.6K 46.4K Vo 22.1K Vreg 31.6K
12/37
L8150
General description
4
4.1
General description
Drive stage
Voltage-controlled PWM drive. Smooth drive architecture (see following dedicated paragraph). External sense resistor as current limiter. FR terminal: Low = Forward, High or Open = Backward.
4.2
Output
U, V, W upper and lower arm power transistors control output (6 outputs) CMOS level (Low: 0V, High: 5V, need output buffer) dead time (0, 1usec, 1.5usec selectable).
4.3
I/O
FG output: multiplexed by Hall signal (open drain) (Hall signal after digital filter are used) Forward/backward control FAULT output: monitor signal for protection operation (low active, open drain), active if one of over voltage, lower voltage, thermal protection, Hall sensor fail protection is operative Torque optimizer: controlled by analog input DM output is the monitor signal of Hall input sequence: - - - IF UVW hall signal sequence is as the direction set by FR, DM=H IF UVW hall signal sequence is opposite for the direction set by FR, DM=L Reset or some case in which UVW sequence can not be monitored, DM=H (Hall signals after digital filter are used for this control).
4.4
Hall Sensor Input Terminals
There are 2 types of application, Hall device and Hall IC Hall Device application: differential inputs with some bias Hall IC application: one input is fixed around VREG/2 by resistor divider between VREG and GND the other input comes from Hall IC whose span is between 0 and 5V.
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General description
L8150
4.5
Protection Functions
- - Over-current protection: Low side current recirculation for both smooth and rectangular drive in normal working condition. Over-voltage protection: compare motor supply VDC (140V, 280V) and IC internal reference. All power transistor OFF (all 6 outputs = GND) during over-voltage. Return to normal operation if VDC is recovered from over-voltage condition. An hysteresis is present.
Lower voltage protection: all power TR OFF (all 6 outputs = GND), if VCC is lower than a defined voltage threshold (All power Transistors OFF if VCC is between 0 to the defined voltage threshold). Return to normal operation if VCC is recovered from lower voltage condition. An hysteresis is present. Thermal protection: all power transistors OFF by external thermal sense signal. If signal is high (exceeds Vth), the power is OFF (all 6 output = GND). Hall sensor fail protection: all power transistor OFF (all output = GND) if Hall signals are HHH or LLL (Hall signals after digital filter are used). Power ON reset (SD): internal logic reset when power ON or recovery from short time Power OFF. All power transistor OFF (all 6 outputs = GND) during reset.
4.6
PWM
carrier frequency: 17-21kHz for Tj = 0 to 125 deg, 18kHz - 20.4kHz for Tj = 25 C.
4.7
System Clock
Internal oscillator: Fsys =1/Tck= 9.8 MHz typical value. One pin for external resistor sets the clock frequency (OSC pin).
4.8
External HVIC Bootstrap Capacitor Initialization
Lower arm ALL ON (3 outputs for low side are High, 3 outputs for High side are GND) when VSP becoming ON (free run release), (while this initialization should not be done when VSP becoming OFF) initializing time is 0.333 - 0.5 msec.
4.9
Package
28 pins SO28. It is suitable for both reflow and flow soldering.
4.10
Others
Upper and lower arm PWM during rectangular drive; it means both side (upper and lower) chopping, not one side chopping, during rectangular drive).
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L8150
General description A maximum current of 5mA can be injected into OV protection terminal in case VCC = OFF and VDC = ON without damaging the device. Moreover the output does not cause malfunctioning (all power Transistors are OFF). A maximum current of 5mA can be injected into TO terminal from external circuit during VCC OFF without damaging the device. The output does not cause malfunctioning (all power Transistors are OFF). A maximum current of 5mA can be injected into INTinN terminal by VSP abnormal operation without damaging the device. The output does not cause malfunctioning (in particular it is needed to avoid VDC short-circuit by Power Transistor cross-conduction). OSC pin sets the main bias currents for the whole device, including system clock.
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Operating description
L8150
5
5.1
Operating description
Free-Run (FS) and Reset (SD) functions
This device does not have an actual startup signal, the working or standby condition depends on two internally-generated signals:

FS signal; SD (shut down) signal.
The first one (FS) is related to the Vsp external signal in the following way. Given the transfer function of the INTAMP network shown below, which is obtained from the suggested INTamp feedback network (see note 6 on Electrical characteristics section): Vo[V] = 5.617V - 0.909 * Vsp[V] we have that when Vsp=1.23V, Vo equals to 4.5V; this signal (amplifier output) is fed to a comparator (FScomp) whose threshold is set at 4.5V (plus some hysteresis). When Vo is greater than 4.5V the device is in the so called "free running" mode, that is all the power outputs are in high impedance; when the threshold is crossed the logic signal FS commutates from High to Low, thus enabling normal device operation. The second one (SD) switches from High to Low, thus enabling normal device operation. When SD is High it acts as a reset signal for the whole logic block and as a stand-by signal for the system oscillator and the speed amplifier. SD = High is generated by a low voltage condition on VREG.
5.2
Smooth Drive and Control logic description
Two basic driving techniques are applied according to different conditions:

rectangular driving sinusoidal driving (Smooth Drive)
The first one is used during startup phase or when the motor is rotating in the opposite direction with respect to FR signal or T>TMAX, while Smooth Drive is used in normal operation. If a DC brushless motor has BEMF voltage with a sinusoidal-like shape, also the currents in the windings are sinusoidal-like, if the applied voltage is sinusoidal. This means that the torque is almost constant and the ripple is very small, allowing acoustic noise reduction and lower EMI. Smooth Drive basically applies three voltage patterns to the motor windings, each 120 electrical degrees out of phase with respect to the other, taking as reference the period measured during the last electrical period. In order to do this, an internal 16-bit counter (Period counter) is provided which is triggered (current value is stored in a register and the counter is reset) at every rising edge of signal coming from U phase Hall sensor (HallU). This kind of behavior is sketched in the picture (Figure 5), where the synchronization control is represented by HallU rising edge. The clock of the counter is the system clock (Fsys) divided by 36: this results in a maximum value of the electrical period that the device can measure and consequently a minimum speed at which Smooth Drive can work; this maximum period is: TMAX = 36*38656*Tck " 141.5 msec, with Tck = 101.7ns (Typical target value)
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L8150 Figure 5. 16 bit counter operation
Operating description
Smooth Drive basic functionality is to apply to the motor the voltage waveforms represented in the following pictures (Figure 6) in case of forward rotation (CW). Figure 6. Smooth drive pattern (forward)
This kind of profile, which realizes waveforms that are differentially sinusoids, is digitally described by a table of 36 8-bit samples stored in a decoding circuit. The final amplitude of the voltage applied on the outputs is obtained by multiplying each sample by a value generated through an 8-bit ADC, whose input is coming from the speed control. The motor is controlled in voltage mode, so no current control compensation network is required. Actuation is done on motor windings through a fixed frequency PWM conversion. Since Smooth Drive is basically a voltage mode driving there can be the need of shifting the applied profile with respect to the BEMF (here sensed through the Hall sensors). This applied phase shift is called Torque Optimizer. The value (expressed in electrical degrees, hereafter referred to as degrees) can be chosen applying an analog voltage to TO pin, that will be internally converted using a 4-bit A/D. The phase shift range is from 2.5 to 40 degrees with a 2.5-degrees step. As a reference the correspondence between phase shift values and analog voltages is reported in Table 21.
17/37
Operating description Table 21. Phase Shift
Analog low threshold [V] <0.20 0.20 0.40 0.60 0.80 0.99 1.19 1.39 1.59 1.78 1.98 2.17 2.37 2.57 2.76 2.96
L8150
Phase Shift [C] 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0
Analog high threshold [V] <0.30 0.30 0.50 0.70 0.89 1.09 1.29 1.49 1.68 1.88 2.08 2.27 2.47 2.66 2.86 3.05
Figure 7.
Phase shift vs input voltage
The 4-bit A/D has an internal hysteresis so that "Analog high thresholds" are the A/D thresholds applying a rising edge on TO pin, the "Analog low thresholds" are the A/D thresholds applying a falling edge on TO pin. The applied phase shift "moves" the voltage profile with respect to the Hall effect sensor in the direction indicated by the arrows in the picture.
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L8150
Operating description In case of reverse rotation (CCW), Smooth Drive applies the voltage profiles represented in the following pictures (Figure 8). Figure 8. Smooth Drive Pattern (Reverse)
HallU
OutU
Phase shift
OutV
OutW
In case sinusoidal mode cannot be applied, a rectangular pattern will be applied, that is driving one phase fixed to GND, one phase in tri-state while the other is switching from low to high with a duty cycle depending on the ADC conversion , max. duty cycle about 95%, according to the following diagram: Figure 9. Rectangular drive pattern (forward)
HallU HallV HallW
OutU
OutV
OutW
The diagram (Figure 9) is showing the applied driving pattern in case of applied torque in forward (continuous blue line) direction, while in case of reverse (continuous red line) direction, the applied pattern can be found in the following picture (Figure 10); in both pictures the meaning of the pattern line is the following: when the line is low, the correspondent winding is driven continuously low; when the line is high, the winding is driven with a duty cycle defined from the ADC conversion at a frequency 512 times slower than the clock. On the other hand, when the line is at middle height the correspondent phase will be left tri-stated.
19/37
Operating description Figure 10. Rectangular Drive Pattern (Reverse)
HallU HallV HallW
L8150
OutU
OutV
OutW
Smooth Drive mode is activated when three consecutive periods shorter than TMAX are detected and device will keep driving in Smooth mode until an external command is applied (through FR pin) or motor electrical period becomes longer than the maximum period the device is able to follow. Startup phase (rectangular driving) is activated in one of the following conditions:

when the Period Counter saturates; when the desired rotation direction (coming from FR command) is different from the detected rotation direction; SD = High Low
During all working conditions a current limitation circuit is active. It is composed of a current comparator sensing current flowing in the sense resistor (usually a sense resistor is connected between the sources of all power low side driver transistors and ground) and of some control logic. Current limitation is achieved in three possible ways according to the different motor situations. The current limiter control method is a consequence of the rotation speed and the detected direction of the motor. Let's divide the possible situations in two different cases: 1. 2. The motor is rotating and its frequency is lower than the one used to switch between rectangular and sinusoidal driving pattern The motor is rotating and its frequency is bigger than the one used to switch between rectangular and sinusoidal driving pattern
In case 1) even if the detected rotation direction is different from the desired direction, the current limiter control method is to force two phases to GND and one phase is left in high impedance state. In case 2) the possible situations can be the following: 2a) The desired direction is equal to the detected direction and sinusoidal mode is applied, the current limiter control method is forcing all the phases to GND
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L8150
Operating description 2b) The desired direction is not equal to the detected direction so that rectangular mode is used, the current limiter control method is forcing all the phases in high impedance state. In any case, current control method is updated every PWM cycle period. The amplitude of the voltage waveform applied to the motor windings allows the control to modulate the rotation speed; this is achieved through an 8-bit analog-to-digital converter (ADC) transforming the output voltage of the control amplifier (INTAMP) into an 8-bit digital word that is used to scale the voltage waveform applied to the motor windings. A digital multiplier, whose inputs are the 8-bit samples of the voltage waveform (that is the output of the 8-bit ADC), gives an 8-bit word that represents the voltage to be applied to the motor winding. Furthermore, control signal actuation is performed through a fixed frequency digital PWM converter, that is converting the 8-bit word coming from the comparator into a digital signal, whose duty cycle is proportional to the resulting voltage to be applied to the motor windings. The period of the PWM output signal is: TPWM = 512 Tck resulting in a frequency that is 19.2 kHz in the typical case. Motor position is detected through a set of three Hall sensor, whose output is differentially fed into the device; after processing the signal by means of a comparator (whose characteristics are explained in the Electrical Characteristics section) the signal is furtherly filtered through a digital circuit to prevent noise from causing any device malfunctioning. The filtering circuit processes signals coming from Hall sensors comparators (HallU, HallV, HallW) and generates a set of three internal signals used inside the digital part of the circuit (PosFil). Figure 11. Filtering circuit
HallU From input comparator HallV HallW Hall sensor filtering block PosFil
3
To control logic
In order to simplify the explanation of the filtering circuit a signal Pos will be defined that can assume 7 different values according to the following table: Table 22.
HallU HallV HallW Pos
7 different values of the signal Pos
1 0 1 p1 1 0 0 p2 1 1 0 p3 0 1 0 p4 0 1 1 p5 0 0 1 p6 0 0 0 pErr
The filtering action takes place according to the following picture (Fig. 7).
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Operating description Figure 12. Filter Block Diagram
Pos
L8150
ck
12 BIT COUNTER
12
>=
12
Reset
Filter Length Latch Enable POS FIL REGISTER PosFil
DELAY 1 Tclk
3
=
PosFil
The filter working principle is explained in the previous diagram (Figure 12): the main component of the filter circuit is a 12-bit counter that is reset (to the value 0) whenever the PosFil signal is equal to the Pos one. When the two signals are different (meaning that a transition is happening), the counter will start counting as long as one of the following conditions will occur:

Pos signal is again equal to former PosFil: in this case a noise is generating some Hall comparator commutation, the counter has reached or overcome the value set by Filter Length signal: in this case the internal Hall signals will be latched into the PosFil register; immediately after this event, PosFil will become equal to Pos and the counter will be reset.
At the same time (at the end of the filtering time), a flip-flop detecting the direction is updated with the right direction information according to the former Hall decoding PosFil and the new one Pos, immediately before latching it into the register. 12-bit Filter Length is set to two values according to different possibilities:
maximum filtering time, corresponding to 4096 clock periods (420us in the typical case, same used for pre-charge function) when an hall effect commutation is detected just after a startup signal edge (SD or FS) and before TMAX/6 is elapsed. This filtering time is also used when the motor accelerate starting from a stopped condition (no hall effect commutation is detected from FS or SD edge to TMAX/6) the filter length is a fraction of the elapsed time between two Zero Crossing signal (ZC). During normal working (in case motor period is shorter than TMAX) it is equivalent to 0.625 electrical degrees. a falling edge of the FS signal is detected a rising edge of the HallU signal is detected any hall effect commutations when the high impedance condition is forced by the IC and the motor is in free-run condition
A ZC signal is produced every time one of these situations happens:

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L8150
Operating description
5.3
Speed Control Circuitry
The rotation speed control signal (VSP) is an external signal, whose range is 2.1V/5.4V. This signal is amplified by an inverting amplifier which takes as reference a voltage derived from VREG through a voltage divider. The amplifier output is the input signal of an 8-bit ADC which generates the digital word KVAL, used to determine the duty cycle value according to the following Figure 13: Speed control: Intout 0-0.7V: duty =100% for smooth drive (max duty is limited at about 95% for rectangular as shown in the following figure) Intout 0.7-3.7V: duty control 100-0% Intout 3.7-4.5: duty = 0 % Intout 4.5V - 5V (VREG): all power off (all 6 output = GND) (Each Vth depends linearly on VREG, being obtained by means of voltage dividers). Figure 13. Duty cycle
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Precharge and hall effects filtering time description
L8150
6
6.1
Precharge and hall effects filtering time description
Startup sequence with FS signal
Let's startup sequence forced by FS comparator, assuming the motor is not rotating:
Figure 14. Startup sequence forced by FS comparator, assuming the motor is not rotating
FS
TelMax/6
PRECHARGE
400 us
ZC
Tzc
Tel
U
HALL BUS
400 us 400 us 400 us 400 us Tzc/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR ACCELERATING
When the signal coming from the FS comparator has a falling edge (corresponding to a Vsp signal crossing the 1.23V threshold), the logic starts counting, to verify if the motor is rotating or not. If the motor is stopped and no Hall effect commutation is detected, the counter has reached its saturation time, given by the following equation: Tel MAX -1 Tel MAX = ( 7MHz ) 141.5msec -------------------- 24msec 6 N.B. TelMAX is equal to TMAX used in the previous sections of this document. After this saturation time the logic has decided to do a precharge function, and for a period of time given by the following equation all the output logic signals UL,VL,WL become high while the signals UH, VH, WH are low. T CHARGE = 4096 T ck 400sec When the precharge is over, the logic outputs start applying the right rectangular pattern to accelerate the motor. During this sequence the Hall filtering time is 400usec until the first rising edge on signal HallU is detected. Then a filter given by the following equation is used: 1 T FILTER = --------- T ZC 576 TZC is the elapsed time between two consecutive zero-crossing signals. By default a zerocrossing signal is generated when a falling edge of the FS comparator is detected, and after that a zero-crossing signal is generated when a rising edge on signal HallU is detected.
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L8150
Precharge and hall effects filtering time description Assumed this operation mode, it is easy to understand that as soon as the startup sequence is over, Hall effects commutations are filtered using a fraction of the electrical period given by the following equation, since TZC is equal to TEL when two consecutive zero-crossing signals generated by a rising edge on signal HallU are detected: 1 1 T FILTER - ROATING = --------- T ZC = --------- T EL 576 576
Let's consider a startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction imposed by the FR signal:
Figure 15. Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction imposed by the FR signal:
FS
ZC
Tzc'
Tzc''
Tel
U
HALL BUS
400 us 400 us Tzc'/576 Tzc'/576 Tzc'/576 Tzc''/576 Tzc''/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR ACCELERATING
When the signal coming from the FS comparator has a falling edge, by default a zerocrossing signal is generated and the logic waits for a Hall effect commutation and applies to it a filtering time of TPRECHARGE=400sec. The first significant zero-crossing signal is generated. Also the second Hall effect commutation is filtered using TPRECHARGE, after that the second zero-crossing signal is generated. Starting from the second Hall effect commutation, after the acquisition of the filtered Hall commutation, the logic outputs start applying the right pattern, and the motor is able to accelerate again. The next filtering time used for the Hall commutation is a fraction of the elapsed time between the first two Hall effect commutations, according to the previous TFILTER equation. This filtering time is used until the first rising edge on signal HallU is detected and a zerocrossing signal is generated. After that the filtering time used is a fraction of the elapsed time between the last two detected zero-crossing signals, in other words between the second Hall effect commutation and the rising edge on signal HallU. Finally, when the second rising edge on signal HallU is detected, the filtering time used is a fraction of the electrical period, as described in previous TFILTER-ROTATING equation.
Let's consider a startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the FR signal:
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Precharge and hall effects filtering time description
L8150
Figure 16. Startup sequence forced by FS comparator, supposing the motor rotating quickly in the direction opposite to that imposed by the FR signal
FS
DM
ZC
Tzc'
HALL BUS
400 us 400 us Tzc'/576 Tzc'/576 Tzc'/576 Tzc'/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR DECELERATING
MOTOR ACCELERATING
This situation is similar to the one described before, except DM behaviour. Let's suppose the FS signal high, which means all phases in high impedance state. Even if the signal FS is high, the logic is able to detect if the motor is rotating in the desired direction or not. So when the signal coming from the FS comparator has a falling edge, by default a zerocrossing signal is generated and the DM signal is already low, indicating that the detected direction is not equal to desired direction. From now on the logic waits for a Hall effect commutation and applies to it a filtering time of TPRECHARGE=400sec. The first significant zero-crossing signal is generated. Also the second Hall effect commutation is filtered using TPRECHARGE, and the second zerocrossing signal is generated. Starting form the second Hall effect commutation, after the acquisition of the filtered Hall commutation, the logic outputs start applying the rectangular pattern, and the motor is able to decelerate until the rotation direction changes becoming equal to the desired one. After the first two Hall commutations, the filtering time used is a fraction of the elapsed time between the first two Hall effect commutations, according to the previous TFILTER equation. This filtering time is used until the first rising edge on signal HallU is detected and a zerocrossing signal is generated. After that the filtering time used is a fraction of the elapsed time between the last two detected zero-crossing signals, in other words between the second Hall effect commutation and the rising edge on signal HallU. Finally, when the second rising edge on signal HallU is detected, the filtering time used is a fraction of the electrical period, as described in previous TFILTER-ROTATING equation. Only when a Hall effect commutation consistent with the desired direction is detected the DM signal becomes high, indicating the right direction detection.
Let's consider a startup sequence forced by FS comparator, supposing the motor rotating too quickly:
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L8150
Precharge and hall effects filtering time description Figure 17. Startup sequence forced by FS comparator, supposing the motor rotating too quickly
FS
Tzc''
ZC
Tzc'
Tzc'
Tel
U
HALL BUS
400 us 400 us 400 us Tzc'/576 Tzc''/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR ROTATING TOO FAST
When the signal coming from the FS comparator has a falling edge, by default a zerocrossing signal is generated and the logic waits for a Hall effect commutation and applies to it a filtering time of TPRECHARGE = 400sec. If the motor is rotating too quickly the next Hall effect commutation happens before the filtering time is elapsed: this causes the reset of the filter and, in consequence, a new count for the filter time of 400sec. Until the motor is rotating too quickly no Hall effect commutation is acquired by the logic, thus the logic outputs force high impedance condition. Only when the motor speed becomes lower than the speed necessary to obtain a Tel/6>400sec the Hall effect commutations are filtered and acquired. If no Hall effect commutation is acquired during a period of TelMax/6, a precharge function will be done. Depending on the last filtered Hall effect codification present in the logic and, also, on the Hall effect codification having a duration longer than 400sec (because the Hall effect codifications filtered have to be consecutive), the Hall effect commutations filtered using a filter time of 400usec could be two or, more probably, three. After this Hall effect commutations the logic outputs start applying the right pattern to the motor windings. The motor rotation direction is irrelevant, in fact this can influence only the kind of pattern applied after the two or three filtered Hall effect commutation.
Let's consider a startup sequence forced by FS-Comparator, supposing the motor rotating slowly.
When the signal coming from the FS comparator has a falling edge, the logic waits for a Hall effect commutation for a period of time equal to TelMAX/6. If no Hall effect commutation happens during this time, the behaviour is the one described in the previous section, when a startup sequence with motor stopped is described. Let's suppose that during the counting period of TelMAX/6 a Hall effect commutation is detected. This commutation is filtered using 400usec. Considering the hypothesis done, starting from the Hall effect commutation detection, no more commutation will be detected
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Precharge and hall effects filtering time description
L8150
for the successive TelMAX/6 and the behaviour is the one described in the startup sequence with motor stopped.
6.2
Startup sequence with SD signal
Let's consider a startup sequence forced by SD, supposing the motor stopped:
Figure 18. Startup sequence forced by SD, supposing the motor stopped
SD
TelMax/6
PRECHARGE
400 us
ZC
Tzc
Tel
U
HALL BUS
400 us 400 us 400 us 400 us Tzc/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR ACCELERATING
When the SD signal has a falling edge (corresponding to a VREG signal that's crossing the lower voltage protection), the logic can produce a ZC signal, depending on FS signal behaviour induced by Vsp voltage value. In any case, even if no ZC signal is produced, if the motor is stopped and no Hall effect commutation is detected, the counter reaches its saturation time TelMAX/6 and the system evolves like in the situation described in previous startup sequence with motor stopped.
Let's consider a startup sequence forced by SD, supposing the motor rotating quickly in the direction imposed by the FR signal:
Figure 19. Startup sequence forced by SD, supposing the motor rotating quickly in the direction imposed by the FR signal
SD
ZC
Tzc
Tel
HALL BUS
400 us 400 us Tzc/576 Tzc/576 Tzc/576 Tzc/576
FILTER TIME
PHASES
PHASES EXCITED
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L8150
Precharge and hall effects filtering time description When the SD signal has a falling edge the logic acquires the Hall codification and waits for next Hall effect commutation, which is filtered using a filtering time of TPRECHARGE = 400sec. The first significant zero-crossing signal is generated. Also the second Hall effect commutation is filtered using TPRECHARGE, after that the second zero-crossing signal is generated. Starting form the second Hall effect commutation, after the acquisition of the filtered Hall commutation, the logic outputs start applying the right pattern, and the motor is able to accelerate again. Next filtering time used for the Hall commutation is a fraction of the elapsed time between the last two zero-crossing signals TDzc. This filtering time is used until the first rising edge on signal HallU is detected and a new zero-crossing signal is generated.
Let's consider a startup sequence forced by SD, supposing the motor rotating quickly in the direction not imposed by the FR signal:
Figure 20. Startup sequence forced by SD, supposing the motor rotating quickly in the direction not imposed by the FR signal
SD
DM
ZC
Tzc
HALL BUS
400 us 400 us Tzc/576 Tzc/576 Tzc/576 Tzc/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR FREE RUN
MOTOR DECELERATING
MOTOR ACCELERATING
This situation is similar to that described before, except DM behaviour. Let's suppose the SD signal high, which means all phases in high impedance state. Since the signal SD is high and considering that this is the reset signal for the whole logic part, the system is not able to detect if the motor is rotating in the desired direction or not and by default the DM signal will be high. So when the signal SD has a falling edge, the DM signal remains high, indicating that the detected direction is equal to desired direction. Only after the first filtered Hall effect commutation the system is able to determines if the rotation direction is equal to the desired one. At this moment the DM signal becomes low. Starting from the second Hall effect commutation, after the acquisition of the filtered Hall commutation, the logic outputs starts applying the right pattern, and the motor starts to decelerate.
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Precharge and hall effects filtering time description
L8150
Only when an Hall effect commutation consistent with the desired direction is detected, the DM signal becomes high, indicating the right direction detection.
Let's consider a startup sequence forced by SD signal, supposing the motor rotating too quickly:
Figure 21. Startup sequence forced by SD signal, supposing the motor rotating too quickly
SD
Tzc''
ZC
Tzc'
Tel
U
HALL BUS
400 us 400 us Tzc'/576 Tzc''/576
FILTER TIME
PHASES EXCITED
PHASES
MOTOR ROTATING TOO FAST
When the SD signal has a falling edge the logic waits for an Hall effect commutation. If the motor is rotating too quickly the next Hall effect commutation occurs before the filtering time has elapsed. This means that a new Hall filter count is performed and no Hall effect codification is acquired until TPRECHARGE has elapsed while the Hall bus is not changed. Until the motor rotates too quickly no Hall effect commutation is acquired by the logic, thus the logic outputs force high impedance condition. Only when the motor speed becomes lower than the speed necessary to obtain a Tel/6>400sec the Hall effect commutation are filtered and acquired. After the first two or three filtered Hall effect commutations (because they have to be consecutive), the logic outputs start applying the right pattern to the motor windings. The motor rotation direction is not important, in fact this can influence only the kind of pattern applied after the two or three filtered Hall effect commutation. In the picture is reported the less likely situation.
Let's consider a startup sequence forced by SD, supposing the motor rotating slowly.
When the signal coming from the SD-Comparator has a falling edge, the logic waits for an Hall effect commutation for a period of time equal to TelMAX/6. If no Hall effect commutation occurs during this time, the behaviour is that described in the previous section, when a startup sequence with motor stopped is described. Let's suppose that during the counting period of TelMAX/6 an Hall effect commutation is detected. This commutation is filtered using 400sec. Considering the hypothesis done, starting from the Hall effect commutation detection, no more commutation will be detected for the following TelMAX/6 and the behaviour is the one described in the startup sequence with motor stopped.
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L8150
Application example
7
Application example
Figure 22. Basic motor control circuit
31/37
Application example Figure 23. 3 phases motor control circuit
L8150
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L8150
Input Output Pins Interface
8
Input Output Pins Interface
In the following the simplified schematics of all the device pins. Figure 24. Pins: TSD, OV, SDT, INTinN, INTinP Figure 25. Pins: TO
VREG
VREG
TSD,OV,SDT, INTinN,INTinP
TO
D01IN1267
D01IN1268
ALWAYS OFF
Figure 26. Pins: RF
Figure 27. Pins: INTout
VREG
VREG
INTout
RF
ACTIVE DURING ADCS SAMPLING
D01IN1269
D01IN1270
Figure 28. Pins: OSC
Figure 29. Pins: FG, DM, FAULT
VREG
VREG
OSC
FG,DM FAULT
D01IN1271
D01IN1272
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Input Output Pins Interface
L8150
Figure 30. ESD clamping
Figure 31. Recirculation diode
VCC
VREG
DEVICE
ESD CLAMP
DEVICE
GND
D01IN1273 D01IN1274
GND
Figure 32. Pins: FR
Figure 33. Pins: HWN, HWP
VREG
VREG
FR
HWN,HWP
On in Test Mode
D01IN1275
D01IN1276
Figure 34. Pins: HUN, HUVP, HVN, HVP
Figure 35. Pins: UH, UL, VH, VL, WH, WL
VREG
VREG
HUN,HUP HVN,HVP
ON DURING POWER UP
D01IN1277
UH,UL VH,VL WH,WL
On in Test Mode
D01IN1278
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L8150
Package information
9
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 36. SO-28 Mechanical data & package dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
OUTLINE AND MECHANICAL DATA
SO-28
8 (max.)
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Revision history
L8150
10
Revision history
Table 23.
Date 20-Mar-2006
Document revision history
Revision 1 Initial release. Changes
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L8150
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